The present invention relates to a novel level shifting circuit which provides immunity to false operation due to unintended transient noise pulses in the circuit.
Level shifting circuits for shifting the potential of a small control signal to a higher or lower voltage level are well known, and are frequently integrated into a power integrated circuit chip. A typical device of this type is the IR2112 sold by the International Rectifier Corporation, the assignee of the present invention. The IR2112 is a high voltage, high speed MOS gated power device for driving the gate of a power MOSFET or insulated gate bipolar transistor (hereinafter an "IGBT"), with independent high side and low side output channels. It has logic inputs supplied by the user of the driver chip. The floating high side channel may be used to drive an N-channel power MOSFET or IGBT which operates off a high voltage rail at up to 600 volts. Hereinafter the term "power MOSFET" is intended to include any MOS gated device including conventional power MOSFETs, IGBTs, thyristors, whether discrete or integrated with the control circuits.
The level shift circuit used in such a high voltage power integrated circuit chip is often implemented with two identical level shift circuit branches--one for set and one for reset--to reduce power dissipation in the chip. In such an implementation, the input logic signal is converted into two narrow pulses at its rising and falling edges. By level shifting these two pulses instead of the logic signal, the level shift circuits are turned on only briefly thereby dissipating much less power.
A possible problem with such a level shift circuit is false operation, that is, production of an output which is not called for by the logic input, under the influence of a noise "glitch" or false pulse. With the set and reset branches being identical, when the circuit is operated under a bias condition at which the circuit starts to lose is functionality, process variation will cause either one of the branches to lose functionality first. When this bias condition for unpredictability is combined with a noise glitch at the input of the chip, the output of both the level shift circuit and the chip can produce unwanted signals.
In an application of the power integrated circuit chip, its output would stay high if only the set branch responds to the input glitch. If the chip was used as a driver for a half bridge or totem-pole arranged power MOSFETs, this will cause an undesirable "shoot-through" condition in the driven half-bridge circuit. A good example of this condition is during the reverse recovery of a half-bridge circuit where the output of the half-bridge falls below the ground at the same time a noise glitch is generated at the input of the driver IC.